Hardware Implementation of 128-Bit AES Image Encryption with Low Power Techniques on FPGA
نویسندگان
چکیده
This paper describes the implementation of a low power and high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to decrease the power using retiming and glitch and operand isolation techniques in four stages, control unit based on logic gates, optimal design of multiplier blocks in mixcolumn phase and simultaneous production keys and rounds. Such procedure makes AES suitable for fast image encryption. Implementation of a 128-bit AES on FPGA of Altera Company has been done, and the results are as follows: throughput, 6.5 Gbps in 441.5 MHz and 130mw power consumption. The time of encrypting in tested image with 32*32 sizes is 1.25ms.
منابع مشابه
FPGA Can be Implemented Using Advanced Encryption Standard Algorithm
This paper mainly focused on implementation of AES encryption and decryption standard AES-128. All the transformations of both Encryption and Decryption are simulated using an iterativedesign approach in order to minimize the hardware consumption. This method can make it avery low-complex architecture, especially in saving the hardware resource in implementing theAES InverseSub Bytes module and...
متن کاملHardware Implementation of Aes Encryption and Decryption for Low Area & Power Consumption
An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilin...
متن کاملFPGA Implementation of JPEG and JPEG2000-Based Dynamic Partial Reconfiguration on SOC for Remote Sensing Satellite On-Board Processing
This paper presents the design procedure and implementation results of a proposed hardware which performs different satellite Image compressions using FPGA Xilinx board. First, the method is described and then VHDL code is written and synthesized by ISE software of Xilinx Company. The results show that it is easy and useful to design, develop and implement the hardware image compressor using ne...
متن کاملFPGA-based Hardware Implementation of Compact AES Encryption Hardware Core
Most of current embedded applications need AES algorithm implementations of small size and low power consumption to assure safe information conveyance. In this article, we present the implementation of a compact ASE hardware encryption core that is suitable for resource-limited applications based on FPGA technology. The core has 8-bit data path structure and supports encryption with 128-bit key...
متن کاملRealization of Advanced Encryption Standard for Power and Area optimization
An AES algorithm can be implemented in software or hardware but hardware implementation is more suitable for high speed applications.AES is most secure security algorithm to maintain safety and reliability of date transmission for this key size is important. And here used AES-256 bit.The main goal of paper is AES hardware implementation to achieve less area and low power consumptions also to ac...
متن کامل